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low power, high speed rail - to - rail input /output amplifier data sheet ad8029 / ad8030/ ad8040 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for a ny infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks an d registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2003C 2012 analog devices, inc. all rights reserved. technical support www.analog.com features qualified for automotive applications low power : 1.3 ma supply current/amplifier high speed 125 mhz, C 3 db bandwidth (g = +1) 60 v/s slew rate 80 ns settling time to 0.1% rail - to - rail input and output no phase reversal, inputs 200 mv beyond rail s wide supply range: 2.7 v to 12 v offset voltage: 6 mv max imum low input bias current +0.7 a to C 1.5 a small packaging soic- 8, sc70 - 6, sot23 - 8, soic - 14, tssop - 14 applications automotive safety and vision systems battery - powered instrumentation filters a- to - d drivers buffering connection diagrams nc = no connect nc 1 ?in 2 +in 3 ?v s 4 disable +v s v out nc 8 7 6 5 03679-a-004 v out 1 ?v s 2 +in 3 5 disable 6 +v s 4 ?in + ? 03679-a-002 figure 1 . soic - 8 (r) figure 2 . sc70 - 6 (ks) v out 1 1 ?in 1 2 +in 1 3 ?v s 4 +v out 2 +v s ?in 2 +in 2 8 7 6 5 03679-a-003 +v s 4 +in 2 5 ?in 2 6 v out 2 7 +in 3 ?v s ?in 3 v out 3 11 10 9 8 v out 1 1 ?in 1 2 +in 1 3 v out 4 ?in 4 +in 4 14 13 12 03679-a-001 figure 3 . soic - 8 (r) and sot23- 8 (rj) figure 4 . soic - 14 (r) and tssop- 14 (ru) general description the ad8029 (single), ad8030 (dual), and ad8040 (quad) are rail - to - rail input and output high speed amplifiers with a quiescent current of only 1.3 ma per amplifier. despite their low power con sumption , the amplifiers provide excellent performance with 125 mhz small signal bandwidth and 60 v/ s slew rate. analog devices, inc., proprietary xfcb process enables high speed and high performance on low power. this family of amplifiers exhibits true single - supply o peration with rail - to - rail input and output performance for supply voltages ranging from 2.7 v to 12 v. the input voltage range extends 200 mv beyond each rail without phase reversal. the dynamic range of the output extends to within 40 mv of each rail. th e ad8029/ad8030/ad8040 provide excellent signal quality with minimal power dissipation. at g = +1, sfdr is C 72 dbc at 1 mhz and settling time to 0.1% is only 80 ns. low distortion and fast settling performance make these amplifiers suitable drivers for sin gle- supply analog - to - digital converters. the versatility of the ad8029/ad8030/ad8040 allows the user to operate the amplifiers on a wide range of supplies while con - suming less than 6.5 mw of power. these features extend the operation time in applications ranging from battery - powered systems with large bandwidth requirements to high speed systems where component density requires lower power dissipation. the ad8040w is an automotive grade version, qualified for automotive applications. the ad8029/ad8030 are the only low power, rail - to - rail input and output high speed amplifiers available in sot23 and sc70 micro packages. the amplifiers are rated over the extended industrial temperature range, C 40c to +125c. time (s) 03679-a-010 voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1s/div g = +1 v s = +5v r l = 1k? tied to midsupply input output figure 5 . rail - to - rail response
important links for the ad8029_8030_8040 * last content update 08/18/2013 10:03 pm parametric selection tables find similar products by operating parameters high speed amplifiers selection table documentation an-649: using the analog devices active filter design tool an-581: biasing and decoupling op amps in single supply applications an-402: replacing output clamping op amps with input clamping amps an-417: fast rail-to-rail operational amplifiers ease design constraints in low voltage high speed systems mt-060: choosing between voltage feedback and current feedback op amps mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to-voltage converters mt-058: effects of feedback capacitance on vfb and cfb op amps mt-056: high speed voltage feedback op amps mt-053: op amp distortion: hd, thd, thd + n, imd, sfdr, mtpr mt-052: op amp noise figure: dont be mislead mt-050: op amp total output noise calculations for second-order system mt-049: op amp total output noise calculations for single-pole system mt-048: op amp noise relationships: 1/f noise, rms noise, and equivalent noise bandwidth mt-047: op amp noise mt-033: voltage feedback op amp gain and bandwidth mt-032: ideal voltage feedback (vfb) op amp a stress-free method for choosing high-speed op amps for the ad8029 ug-112: universal evaluation board for single, high speed op amps offered in sc-70 packages ug-101: evaluation board user guide for the ad8030 ug-019: universal evaluation board for dual, high speed op amps offered in 8-lead sot-23 packages ug-128: universal evaluation board for dual high speed op amps in soic packages for the ad8040 ug-111: universal evaluation board for quad, high speed op amps offered in 14-lead soic packages ug-020: universal evaluation board for quad high speed op amps offered in 14-lead tssop packages design tools, models, drivers & software dbm/dbu/dbv calculator analog filter wizard 2.0 power dissipation vs die temp adisimopamp? opamp stability ad8029 spice macro model ad8030 spice macro model ad8040 spice macro model evaluation kits & symbols & footprints view the evaluation boards and kits page for the ad8029 view the evaluation boards and kits page for the ad8030 view the evaluation boards and kits page for the ad8040 symbols and footprints for the ad8029 symbols and footprints for the ad8030 symbols and footprints for the ad8040 design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad8029 ad8030 ad8040 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad8029/ad8030/ad8040 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? connection diagrams ...................................................................... 1 ? general description ......................................................................... 1 ? specifications ..................................................................................... 3 ? specifications with 5 v supply ................................................. 3 ? specifications with +5 v supply ................................................. 4 ? specifications with +3 v supply ................................................. 5 ? absolute maximum ratings ............................................................ 7 ? maximum power dissipation ..................................................... 7 ? esd caution .................................................................................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 16 ? input stage ................................................................................... 16 ? output stage ................................................................................ 16 ? applications ..................................................................................... 17 ? wideband operation ................................................................. 17 ? output loading sensitivity ....................................................... 17 ? disable pin .................................................................................. 18 ? circuit considerations .............................................................. 19 ? design tools and technical support ....................................... 19 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 21 ? revision history 10/12rev. a to rev. b added automotive model, ad8040w ............................ universal changes to features section............................................................ 1 changes to general description section ...................................... 1 changes to specifications section, table 1, added automotive specifications ..................................................................................... 3 moved esd caution to absolute maximum ratings section .... 7 changes to figure 17 ........................................................................ 9 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 21 11/03rev. 0 to rev. a added ad8040 part ....................................................... universal change to figure 5 ....................................................................... 1 changes to specifications ............................................................ 3 changes to figures 10C12 ............................................................ 7 change to figure 14 ..................................................................... 8 changes to figures 20 and 21 ..................................................... 9 inserted new figure 36 ............................................................... 11 change to figure 40 ................................................................... 12 inserted new figure 41 ............................................................... 12 added output loading sensitivity section ............................. 16 changes to table 5 ...................................................................... 17 changes to power supply bypassing section .......................... 18 changes to ordering guide ...................................................... 20
data sheet ad8029/ad8030/ad8040 rev. b | page 3 of 24 specifications specifications with 5 v supply table 1. v s = 5 v @ t a = 25c, g = +1, r l = 1 k to ground, unless otherwise noted. all specifications are per amplifier. parameter conditions min typ max unit dynamic performance C3 db bandwidth g = +1, v o = 0.1 v p-p 80 125 mhz ad8040w only: t min to t max 80 mhz g = +1, v o = 2 v p-p 14 19 mhz ad8040w only: t min to t max 9 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.1 v p-p 6 mhz slew rate g = +1, v o = 2 v step 62 v/s g = C1, v o = 2 v step 63 v/s settling time to 0.1% g = +2, v o = 2 v step 80 ns noise/distortion performance spurious free dynamic range (sfdr) f c = 1 mhz, v o = 2 v p-p C74 dbc f c = 5 mhz, v o = 2 v p-p C56 dbc input voltage noise f = 100 khz 16.5 nv/ hz input current noise f = 100 khz 1.1 pa/ hz crosstalk (ad8030/ad8040) f = 5 mhz, v in = 2 v p-p C79 db dc performance input offset voltage pnp active, v cm = 0 v 1.6 5 mv ad8040w only: t min to t max 9.5 mv npn active, v cm = 4.5 v 2 6 mv ad8040w only: t min to t max 9.5 mv input offset voltage drift t min to t max 30 v/c input bias current 1 npn active, v cm = 4.5 v 0.7 1.3 a t min to t max 1 a ad8040w only: t min to t max 1.3 a pnp active, v cm = 0 v C1.7 C2.8 a t min to t max 2 a ad8040w only: t min to t max C2.8 a input offset current 0.1 0.9 a ad8040w only: t min to t max 0.9 a open-loop gain v o = 4.0 v 65 74 db ad8040w only: t min to t max 62 db input characteristics input resistance 6 m input capacitance 2 pf input common-mode voltage range C5.2 to +5.2 v common-mode rejection ratio v cm = C4.5 v to +3 v, r l = 10 k 80 90 db ad8040w only: t min to t max 80 db disable pin (ad8029) disable low voltage Cv s + 0.8 v disable low current C6.5 a disable high voltage Cv s + 1.2 v disable high current 0.2 a turn-off time 50% of disable to <10% of final v o , v in = C1 v, g = C1 150 ns turn-on time 50% of disable to <10% of final v o , v in = C1 v, g = C1 85 ns output characteristics output overdrive recovery time (rising/falling edge) v in = +6 v to C6 v, g = C1 55/45 ns output voltage swing r l = 1 k Cv s + 0.22 +v s C 0.22 v ad8040w only: t min to t max Cv s + 0.22 +v s C 0.22 v r l = 10 k Cv s + 0.05 +v s C 0.05 v ad8040w only: t min to t max Cv s + 0.05 +v s C 0.05 v
ad8029/ad8030/ad8040 data sheet rev. b | page 4 of 24 parameter conditions min typ max unit short - circ uit current sinking and sourcing 170/160 ma off isolation (ad8029) v in = 0.1 v p - p, f = 1 mhz, disable = low C 55 db capacitive load drive 30% overshoot 20 pf power supply operating range 2.7 12 v quiescent current/ampli fier 1.4 1.5 ma ad8040w only: t min to t max 1.85 ma quiescent current (disabled) disable = low , ad8029 only 150 200 a power supply rejection ratio v s 1 v 73 80 db ad8040w only: t min to t max 72 db 1 plus, +, (or no sign) i ndicates current into pin; minus ( C ) indicates current out of pin. specifications with +5 v supply table 2 . v s = 5 v @ t a = 25c, g = +1, r l = 1 k ? to midsupply, unless otherwise noted. all specifications are per amplifier. parameter conditions min typ max unit dynamic performance C 3 db bandwidth g = +1, v o = 0.1 v p -p 80 120 mhz ad8040w only: t min to t max 80 mhz g = +1, v o = 2 v p - p 13 18 mhz ad8040w only: t min to t max 8 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.1 v p -p 6 mhz slew rate g = +1, v o = 2 v step 55 v/s g = C 1, v o = 2 v step 60 v/s settling time to 0.1% g = +2, v o = 2 v step 82 ns noise/distortion performance spurious free dynamic range (sfdr) f c = 1 mhz, v o = 2 v p -p C73 dbc f c = 5 mhz, v o = 2 v p -p C55 dbc input voltage noise f = 100 khz 16.5 nv/ hz input current noise f = 100 khz 1.1 pa/ hz crosstalk (ad8030/ad8040) f = 5 mhz, v in = 2 v p -p C79 db dc performance input offset voltage pnp active, v cm = 2.5 v 1.4 5 mv ad8040w only: t min to t max 8.5 mv npn active, v cm = 4.5 v 1.8 6 mv ad8040w only: t min to t max 8.5 mv input offset voltage drift t min to t max 25 v/c input bias current 1 npn active, v cm = 4.5 v 0.8 1.2 a t min to t max 1 a pnp active, v cm = 2.5 v C 1.8 C 2.8 a t min to t max 2 a input offset current 0.1 0.9 a ad8040w only: t min to t max 0.9 a open - loop gain v o = 1 v to 4 v 65 74 db ad8040w only: t min to t max 62 db input characteristics input resistance 6 m? input capacitance 2 pf input common - mode voltage range C 0.2 to +5.2 v common - mode rejection ratio v cm = 0.25 v to 2 v, r l = 10 k? 80 90 db ad8040w only: t min to t max 80 db disable pin (ad8029) disable low voltage Cv s + 0.8 v disable low current C 6.5 a disable high voltage Cv s + 1.2 v
data sheet ad8029/ad8030/ad8040 rev. b | page 5 of 24 parameter conditions min typ max unit disable high current 0.2 a turn - off time 50% of disable to <10% of final v o , v in = C 1 v, g = C1 155 ns turn - on time 50% of disable to <10% of final v o , v in = C 1 v, g = C1 90 ns output characteristics overdrive recovery time (rising/fa lling edge) v in = C 1 v to +6 v, g = C1 45/50 ns output voltage swing r l = 1 k? Cv s + 0.17 +v s C 0.17 v ad8040w only: t min to t max Cv s + 0.17 +v s C 0.17 v r l = 10 k? Cv s + 0.04 +v s C 0.04 v ad8040w only: t min to t max Cv s + 0.04 +v s C 0.04 v short- circuit current sinking and sourcing 95/60 ma off isolation (ad8029) v in = 0.1 v p - p, f = 1 mhz, disable = low C55 db capacitive load drive 30% overshoot 15 pf power supply operating range 2.7 12 v quiescent curren t/amplifier 1.3 1.5 ma ad8040w only: t min to t max 1.75 ma quiescent current (disabled) disable = low, ad8029 only 140 200 a power supply rejection ratio v s 1 v 73 80 db ad8040w only: t min to t max 72 db 1 plus, +, (or no sign) indicates current into pin; minus ( C ) indicates current out of pin. specifications with +3 v supply table 3 . v s = +3 v @ t a = 25c, g = +1, r l = 1 k ? to midsupply, unless otherwise noted. all specifications are per amplifier. parameter conditions min typ max unit dynamic performance C 3 db bandwidth g = +1, v o = 0.1 v p -p 80 112 mhz ad8040w only: t min to t max 80 mhz g = +1, v o = 2 v p -p 13 18 mhz ad8040w only: t min to t max 8 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.1 v p -p 6 mhz slew rate g = +1, v o = 2 v step 55 v/s g = C 1, v o = 2 v step 57 v/s settling time to 0.1% g = +2, v o = 2 v step 110 ns noise/distortion performance spurious free dynamic range (sfdr) f c = 1 mhz, v o = 2 v p-p C72 dbc f c = 5 mhz, v o = 2 v p - p C 60 dbc input voltage noise f = 100 khz 16.5 nv/ hz input current noise f = 100 khz 1.1 pa/ hz crosstalk (ad8030/ad8040) f = 5 mhz, v in = 2 v p -p C80 db dc per formance input offset voltage pnp active, v cm = 1.5 v 1.1 5 mv ad8040w only: t min to t max 8 mv npn active, v cm = 2.5 v 1.6 6 mv ad8040w only: t min to t max 8 mv input offset voltage drift t min to t max 24 v/c input bias current 1 npn a ctive, v cm = 2.5 v 0.7 1.2 a t min to t max 1 a input bias current 1 pnp active, v cm = 1.5 v C 1.5 C 2.5 a t min to t max 1.6 a input offset current 0.1 0.9 a ad8040w only: t min to t max 0.9 a
ad8029/ad8030/ad8040 data sheet rev. b | page 6 of 24 parameter conditions min typ max unit open - loop gain v o = 0.5 v to 2.5 v 64 73 db ad8040w only: t min to t max 62 db input characteristics input resistance 6 m? input capacitance 2 pf input common - mode voltage range C 0.2 to +3.2 v common - mode rejection ratio v cm = 0.25 v to 1.25 v, r l = 10 k? 78 88 db ad8040 w only: t min to t max 78 db disable pin (ad8029) disable low voltage Cv s + 0.8 v disable low current C 6.5 a disable high voltage Cv s + 1.2 v disable high current 0.2 a turn - off time 50% of disable to <10% of final v o , v in = C 1 v, g = C1 165 ns turn - on time 50% of disable to <10% of final v o , v in = C 1 v, g = C1 95 ns output characteristics outp ut overdrive recovery time (rising/falling edge) v in = C 1 v to +4 v, g = C1 75/100 ns output voltage swing r l = 1 k? Cv s + 0.09 +v s C 0.09 v ad8040w only: t min to t max Cv s + 0.09 +v s C 0.09 v r l = 10 k? Cv s + 0.04 +v s C 0.04 v ad8040w o nly: t min to t max Cv s + 0.04 +v s C 0.04 v short- circuit current sinking and sourcing 80/40 ma off isolation (ad8029) v in = 0.1 v p - p, f = 1 mhz, disable = low C55 db capacitive load drive 30% overshoot 10 pf power supply operating range 2.7 12 v quiescent current/amplifier 1.3 1.4 ma ad8040w only: t min to t max 1.75 ma quiescent current (disabled) disable = low, ad8029 only 145 200 a power supply rejection ratio v s 1 v 70 76 db ad8040w on ly: t min to t max 68 db 1 plus, +, (or no sign) indicates current into pin; minus ( C ) indicates current out of pin.
data sheet ad8029/ad8030/ad8040 rev. b | page 7 of 24 absolute maximum rat ings table 4 . ad8029/ad8030/ad8040 stress ratings parameter rating supply voltage 12.6 v po wer dissipation see figure 6 common - mode input voltage v s 0.5 v differential input voltage 1.8 v storage temperature C 65c to +125c operating temperature range C 40c to +125c lead temperature range (sold ering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above th ose indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissip ation the maximum safe power dissipation in the ad8029/ad8 030/ ad8040 package is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die locally reaches the junction temperature. at approximately 150c, which is the glass transition temperature, the plastic change s its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8029/ad8030/ad8040. exceeding a junction temperature of 175c for an ex tended period can result in changes in silicon devices, potentially causing failure. the still - air thermal properties of the package and pcb ( ja ), ambient temperature ( t a ), and the total power dissipated in the package ( p d ) determine the junction tempera ture of the die. the junction temperature can be calculated as t j = t a + (p d ja ) the power dissipated in the package ( p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the qu iescent power is the voltage between the supply pins ( v s ) times the quiescent current ( i s ). assuming the load ( r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load (v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. p d = quiescent power + ( total drive power C load power ) ( ) l out l out s ss d r v r v v ivp 2 C 2 ? ? ? ? ? ? ? ? += rms output voltages should be considered. if r l is referenced t o v s C , as in single - supply operation, then the total drive power is v s i out . if the rms signal levels are indeterminate, consider the worst case, when v out = v s /4 for r l to midsupply: ( ) ( ) l s ss d r v ivp 2 4/ += in single - supply operation with r l referenced t o v s C , worst case is v out = v s /2. airflow increase s heat dissipation, effectively reducing ja . also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the ja . care must be tak en to minimize parasitic capaci tances at the input leads of high speed op amps, as discuss ed in the pcb layout section. figure 6 shows the maximum safe power dissipation in the package versus the ambient temperature for the soic - 8 (125c/w), sot23 - 8 (160c/w), s oic - 14 (90c/w), tssop - 14 (120c/w), and sc70 - 6 (20 8c/w) packages on a jedec standard 4 - layer board. ja values are approximations. ?40 ?20 ?10 ?30 0 10 20 30 40 50 60 70 80 90 100 110 120 2.5 maximum power dissipation (w) 1.0 0.5 1.5 2.0 0 ambient temperature (c) soic-8 tssop-14 soic-14 sot-23-8 sc70-6 03679-a-018 figure 6 . maximum power dissipation output short circuit shorting the output to ground or drawing excessive current from the ad8029/ad8030/ad8040 could cause catastrophic failure. esd caution
ad8029/ad8030/ad8040 data sheet rev. b | page 8 of 24 typical performance characteristics default conditions: v s = 5 v (t a = 25c, r l = 1 k? tied to midsupply, unless otherwise noted.) frequency (mhz) 0.1 1 10 100 1000 ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 normalized closed-loop gain (db) 03679-0-004 g = +10 r f = 9k?, r g = 1k? g = +2 r f = r g = 1k? g = ?1 r f = r g = 1k? v o = 0.1v p-p g = +1 r f = 0? figure 7 . small signal frequency response f or various gains frequency (mhz) 1 10 100 1000 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 closed-loop gain (db) 03679-0-005 5v +5v +3v g = +1 v o = 0.1v p-p figure 8 . small signal frequency response for various supplies frequency (mhz) 1 10 100 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 closed-loop gain (db) 03679-0-006 5v +5v +3v g = +1 v o = 2v p-p figure 9 . large signal frequency response for various supplies frequency (mhz) 1 10 100 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 normalized closed-loop gain (db) 03679-a-011 dashed lines: v out = 2v p-p solid lines: v out = 0.1v p-p g = +1 g = +2 r f = 1k? figure 10 . 0.1 db flatne ss frequency response frequency (mhz) 1 10 100 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 normalized closed-loop gain (db) 03679-a-012 5v +3v +5v g = +2 v o = 0.1v p-p r f = 1k? figure 11 . small signal frequency response for various supplies frequency (mhz) 1 10 100 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 normalized closed-loop gain (db) 03679-a-013 v s = 5 v s = +3 v s = +5 g = +2 v o = 2v p-p r f = 1k? figure 12 . large signal frequency response for various supplies
data sheet ad8029/ad8030/ad8040 rev. b | page 9 of 24 frequency (mhz) 1 10 100 1000 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 closed-loop gain (db) 03679-0-010 0pf 20pf 10pf 5pf g = +1 v o = 0.1v p-p figure 13 . small signal frequency response for various c load frequency (mhz) 1 10 100 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 normalized closed-loop gain (db) 03679-a-014 2v p-p 1v p-p 0.1v p-p g = +2 r f = 1k? figure 14 . frequency response for various output amplitudes 03679-0-054 10 100 1k 10k 100k 1m 10m 100m 1g 80 70 60 225 180 135 90 45 0 50 40 open-loop gain (db) open-loop phase (degrees) 30 20 10 0 ?10 ?20 frequency (hz) figure 15 . open - loop gain and phase vs. frequency frequency (mhz) 1 10 100 1000 03679-0-013 closed-loop gain (db) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 g = +1 v o = 0.1v p-p v icm = 0v v icm = v s+ ? 0.2v v icm = v s? + 0.2v figure 16 . sm all signal frequency response for various input common - mode voltages frequency (mhz) 1 100 10 1000 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 closed-loop gain (db) 03679-0-014 +125 c +85 c +25 c ?40 c g = +1 v o = 0.1v p-p figure 17 . small signal frequency response vs. temperature frequency (mhz) 1 10 100 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 closed-loop gain (db) 03679-0-015 +125c +25c +85c ?40c g = +1 v o = 2v p-p figure 18 . large signal frequency response vs. temperature
ad8029/ad8030/ad8040 data sheet rev. b | page 10 of 24 frequency (mhz) 03679-0-016 0.01 0.1 10 1 harmonic distortion (dbc) ?105 ?95 ?85 ?75 ?65 ?55 ?45 ?35 g = +1 v out = 2v p-p r l = 1k? second harmonic: solid line third harmonic: dashed line v s = +3v v s = +5v v s = 5v figur e 19 . harmonic distortion vs. frequency and supply voltage 03679-a-015 harmonic distortion (dbc) ?80 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 output amplitude (v p-p) g = +2 freq = 1mhz r f = 1k? second harmonic: solid line third harmonic: dashed line v s = +3v v s = +5v v s = +10v figure 20 . harmonic distortion vs. output amplitude frequency (mhz) 0.01 0.1 1 10 harmonic distortion (dbc) ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 03679-a-016 second harmonic: solid line third harmonic: dashed line v s = +5v v out = 2.0v p-p r l = 1k? r f = 1k? g = +2 g = +1 g = ?1 figure 21 . harmonic distortion vs. frequency and gain frequency (mhz) 0.01 0.1 1 10 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 03679-0-075 harmonic distortion (dbc) g = +1 v out = 2v p-p second harmonic: solid line third harmonic: dashed line r l = 1k? r l = 2k? r l = 5k? fi gure 22 . harmonic distortion vs. frequency and load input common-mode voltage (v) 03679-0-020 1.0 1.5 2.0 2.5 3.0 3.5 4.0 harmonic distortion (dbc) ?100 ?90 ?80 ?70 ?60 ?50 ?40 g = +1 v out = 2v p-p freq = 1mhz second harmonic: solid line third harmonic: dashed line v s = +3v v s = +5v figure 23 . harmonic distortion vs. input common mode voltage frequency (hz) 10 100 1k 10k 100k 1m 10m 1 10 100 1000 0.1 1 10 100 03679-0-069 voltage noise (nv/ hz) current noise (pa/ hz) voltage noise current noise figure 24 . voltage and current noise vs. frequency
data sheet ad8029/ad8030/ad8040 rev. b | page 11 of 24 ?100 time (ns) ?75 ? 50 ?25 25 0 output voltage (mv) 50 75 100 g = +1 v s = 2.5v 20ns/div 25mv/div 03679-0-022 fi gure 25 . small signal transient response 03679-a-023 time (ns) output voltage (v) ?2.5 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0.5v/div 25ns/div g = +1 v s = 2.5v 2v p-p 4v p-p figure 26 . large signal transient response ?4 ?3 ?2 ?1 1 0 2 3 4 g = ?1 (r f = 1k?) r l = 1k? v s = 2.5v 200ns/div 1v/div 03679-0-024 input output time (ns) output voltage (v) figure 27 . output overdrive recovery ?100 ?75 ?50 ?25 25 0 50 75 100 g = +1 v s = 2.5v 20ns/div 25mv/div 03679-0-025 c l = 20pf c l = 5pf c l = 10pf time (ns) output voltage (mv) figure 28 . small sig nal transient response with capacitive load 03679-0-059 voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (seconds) 1s/div g = +1 v s = +5v r l = 1k? tied to midsupply input output figure 29 . rail - to - rail response, g = +1 ?4 ?3 ?2 ?1 1 0 2 3 4 g = +1 r l = 1k? v s = 2.5v 200ns/div 1v/div 03679-0-027 input output time (ns) output voltage (v) figure 30 . input overdrive recovery
ad8029/ad8030/ad8040 data sheet rev. b | page 12 of 24 ?0.1% +0.1% 500ns/div 03679-0-062 v out ? 2v in (0.1%/div) g = +2 v s = 2.5v +1v ?1v v out (500mv/div) figure 31 . long - term settling time frequency (hz) 1k 10k 100k 1m 10m 100m 1g ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 03679-0-078 cmrr (db) figur e 32 . common - mode rejection ratio vs. frequency 03679-0-055 0.1 1 10 100 1000 ?20 output (db) ?70 ?60 ?50 ?40 ?30 ?80 frequency (mhz) g = +1 r l = 1k? disable = low v in = 0.1v p-p figure 33 . ad8029 off - isolation vs. frequency ?0.1% +0.1% 20ns/div 03679-0-063 v out ? 2v in (0.1%/div) v out (500mv/div) v in (250mv/div) g = +2 figure 34 .0.1% short - term settling time 1k 10k 100k 1m 10m 100m 1g frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 03679-0-033 +psrr ?psrr figure 35 . psrr vs. frequency 03679-a-005 frequency (mhz) crosstalk (db) 0.01 ?130 1000 0.1 1.0 10 100 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 drive amp 1k? 50? v in crosstalk = 20log ( v out v in ) listen amp 1k? v out ad8040 (amp 4 drive amp 1 listen) ad8030 (amp 2 drive amp 1 listen) figure 36 . ad8030/ad8040 crosstalk vs. frequency
data sheet ad8029/ad8030/ad8040 rev. b | page 13 of 24 input common-mode voltage (v) ?1 0 1 2 3 4 5 6 7 8 9 10 11 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 03679-0-074 input bias current (a) v s = +3v v s = +5v v s = +10v figure 37 . input bias current vs. input common - mode voltage temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 ?2.0 ?1.0 ?1.2 ?1.4 ?1.6 ?1.8 0 1.0 0.8 0.6 0.4 0.2 03679-0-073 input bias current (pnp active) (a) input bias current (npn active) (a) v s = +3 v s = +5 v s = 5 npn active pnp active figure 38 . input bias current vs. te mperature temperature (c) supply current (ma) ?40 ?20 0 20 40 60 80 100 120 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 03679-0-067 v s = 5v v s = +5v v s = +3v figure 39 quiescent supply current vs. temperature input common-mode voltage (v) input offset voltage (mv) ?1 0 1 2 3 4 5 6 7 8 9 10 11 ?4 ?3 ?2 ?1 0 1 2 3 4 03679-a-017 v s = +3v v s = +5v v s = +10v r l = 1k? to midsupply g = +1 figure 40 . input offset voltage vs. input common - mode voltage 03679-a-006 temperature (c) input offset voltage (mv) ?4 125 ?40 ?25 ?10 5 20 35 50 65 80 95 110 v s = 5v v s = +5v v s = +3v 4 3 2 1 0 ?1 ?2 ?3 figure 41 . input offset voltage vs. temper ature input offset voltage (mv) frequency ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0 20 40 60 80 100 120 03679-0-064 count = 1088 mean = 0.44mv stdev = 1.05mv figure 42 . input offset voltage distribution
ad8029/ad8030/ad8040 data sheet rev. b | page 14 of 24 03679-0-061 100k 1m 10m 100m 1g output impedance (?) 1 10 100 1k 1m 100k 10k frequency (hz) disable = low figure 43 . ad8029 output impedance vs. frequency, disabled load resistance (?) output saturation voltage (v) 100 1000 10000 ?0.5 0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 v s = +3v v s = +5v v s = 5v v oh ? v s v ol ? v s load resistance tied to midsupply 03679-0-041 figure 44 . output saturation voltage vs. load resistance temperature (c) output saturation voltage (mv) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 30 50 70 90 110 130 150 170 03679-0-066 v s = 5v v s = +5v v s = +3v r l = 1k? tied to midsupply solid line: v s+ ? voh dashed line: vol ? v s? figure 42. output saturation voltage vs. temperature 03679-0-060 1k 10k 100k 1m 10m 100m 1g output impedance (?) 0.1 1 10 100 1000 frequency (hz) g = +1 figure 45 . output impedance vs. frequency, enabled output voltage (v) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 ?0 0.5 1.0 1.5 2.0 2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 03679-0-072 input error voltage (mv) r l = 10k? r l = 1k? v s = 2.5v figure 46 . input error voltage vs. output voltage
data sheet ad8029/ad8030/ad8040 rev. b | page 15 of 24 03679-a-020 0 50 100 150 200 250 300 350 1.5 output amplitude (v) ?1.0 ?0.5 0 0.5 1.0 ?1.5 time (ns) disable (?0.5v to ?2v) r l = 10k? r l = 100? r l = 1k? v s = 2.5v g = ?1 (r f = 1k?) output disabled figure 47 . ad8029 disable turn- off timing 03679-a-021 0 50 100 150 200 250 300 350 1.5 output amplitude (v) ?1.5 ?1.0 ?0.5 0 0.5 1.0 time (ns) disable (?2v to ?0.5v) r l = 100? r l = 1k? r l = 10k? v s = 2.5v g = ?1 (r f = 1k?) output enabled figure 48 . ad8029 disable turn- on timing disable pin voltage (v) v s = +3v, +5v, +10v 0 10.8 1.2 2 3 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 03679-a-022 disable pin current (a) figure 49 . ad8029 disable pin current vs. disable pin voltage
ad8029/ad8030/ad8040 data sheet rev. b | page 16 of 24 theory of operation 03679-0-051 in? in+ r 5 r 6 r 7 r 8 r 1 r 2 r 3 r 4 m top i tail m bot output buffer ?v s r th i th +v s ?1.2v +v s v out q 10 q 11 c mt c mb ?v s ad8029 only to disable circuitry disable q 3 q 4 q 2 q 1 q 9 q 8 q 7 q 6 q 5 out in com spd figure 50 . simplified schematic the ad8029 (single), ad8030 (dual), and ad8040 (quad) are rail - to - rail input and output amplifiers fabricated using analog devices xfcb process. the xfcb process enables the ad8029/ ad8030/ad8040 to operate on 2.7 v to 12 v supplies with a 120 mhz bandwidth and a 60 v/s slew rate. a simplified sche - matic of the ad8029/ad8030/ad8040 is shown in figure 50. input stage for input common - mode voltages less than a set threshold (1.2 v below v cc ), the resistor degenerated pnp differential pair (comprising q 1 toq 4 ) carries the entire i tail current, allowing the input voltage to go 200 mv below Cv s . c onversely, input common - mode voltages exceeding the same threshold cause i tail to be routed away from the pnp differential pair and into the npn differential pair through transistor q 9 . under this condition, the input common - mode voltage is allowed to rise 200 mv above +v s while still maintaining linear amplifier behavior. the transition between these two modes of operation leads to a sudden, temporary shift in input stage transconduc - tance, g m , and dc parameters (such as the input offset voltage v os ), whic h in turn adversely affect the distortion performance. the spd block shortens the duration of this transition, thus improving the distortion performance. as shown in figure 50, the input differential pair is protected by a pair of two series diodes, connected in anti - parallel, which clamp the differential input voltage to approximately 1.5 v. output stage the currents derived from the pnp and npn input differential pairs are injected into the current mirrors m bot and m top , thus establishing a common - mode signal voltage at the input of the output buffer. the output buffer performs three functions: 1. it buffers and applies the desired signal voltage to the output devices, q 10 and q 11 . 2. it senses the common - mode current level in the output devices. 3. it regulates the output common - mode current by establishing a common - mode feedback loop. the output devices q 10 and q 11 work in a common - emitter configuration, and are miller - compensated by internal capacitors, c mt and c mb . the output voltage compliance is set by the output devices collector resistance r c (about 25 ?), and by the required load current i l . for instance, a light equivalent load (5 k?) allows the output voltage to swing to within 40 mv of either rail, while heavier loads cause this figure to deteriorate as r c i l .
data sheet ad8029/ad8030/ad8040 rev. b | page 17 of 24 applications wideband oper ation +v s ?v s c2 10f c1 0.1f c4 0.1f c3 10f v out + ? ad8029 r g r1 r f disable v in r1 = r f ||r g 03679-0-052 figure 51 . wideband non - inverting gain configuration +v s ?v s c1 0.1f c4 0.1f c3 10f r1 v out ? + ad8029 r g r1 = r f ||r g r f v in 03679-0-053 c2 10f disable figure 52 . wideband inverting gain configuration output loading s ensitivity to achieve maximum performance and low power dissipation, the des igner needs to consider the loading at the output of ad8029/ad8030/ad8040. table 5 shows the effects of output loading and performance. when operating at unity gain, the effective load at the amplifier output is the resistance (r l ) being driven by the amplifier. for gains other than 1, in noninverting configurations, the feedback network represents an additional current load at the amplifier output. the feedback network (r f + r g ) is in parallel with r l , which lowers the effective resistance at the output of the amplifier. the lower effective resistance causes the amplifier to supply more current at the output. lower values of feedback resistance increase the current draw, thus increasing the amplifiers power dissipat ion. for example, if using the values shown in table 5 for a gain of 2, with resistor values of 2.5 k?, the effective load at the output is 1.67 k?. for inverting configurations, only the feedback resistor r f is in parallel with the output load. if the load is greater than that specified in the data sheet, the amplifier can introduce nonlinearities in its open - loop response, which increases distortion. figure 53 and figure 54 illustrate effective output loading and distortion performance. increasing the resistance of the feedback network can reduce the current consumption, but has other implications. frequency (mhz) harmonic distortion (dbc) 0.01 ?120 0.1 1.0 10 03679-a-008 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 v s = 5v v out = 0.1v p-p r l = 5k? r l = 2.5k? v s = 5v v out = 2.0v p-p second harmonic ? solid lines third harmonic ? dotted lines r l = 1k? figure 53 . gain of 1 distortion frequency (mhz) harmonic distortion (dbc) 0.01 ?120 0.1 1.0 10 03679-a-009 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 v s = 5v v out = 0.1v p-p r f = r l = 1k? v s = 5v v out = 2.0v p-p second harmonic ? solid lines third harmonic ? dotted lines r f = r l = 5k? r f = r l = 2.5k? figure 54 . gain of 2 distortion
ad8029/ad8030/ad8040 data sheet rev. b | page 18 of 24 table 5 . effect of load on performance noninverting gain r f (k?) r g (k?) r load (k?) C 3 db ss bw (mhz) peaking (db) hd2 at 1 mhz, 2 v p - p (db) h d3 at 1 mhz, 2 v p - p (db) output noise (nv/hz) 1 0 n/a 1 120 0.02 C80 C72 16.5 1 0 n/a 2 130 0.6 C84 C83 16.5 1 0 n/a 5 139 1 C 87.5 C 92.5 16.5 2 1 1 1 36 0 C72 C60 33.5 2 2.5 2.5 2.5 44.5 0.2 C79 C72.5 34.4 2 5 5 5 43 2 C84 C86 36 C1 1 1 1 40 0.01 C68 C57 33.6 C1 2.5 2.5 2.5 40 0.05 C74 C68 34 C1 5 5 5 34 1 C78 C80 36 the feedback resistance (r f || r g ) combines with the input capacitance to form a pole in the amplifiers loop response. this can cause peaking and ringing in the amplifiers respo nse if the rc time constant is too low. figure 55 illustrates this effect. peaking can be reduced by adding a small capacitor (1 pf C4 pf) across the feedback resistor. the best way to find the optimal value of capac itor is to empirically try it in your circuit. another factor of higher resistance values is the impact it has on noise performance. higher resistor values generate more noise. each application is unique and therefore a balance must be reached between dist ortion, peaking, and noise performance. table 5 outlines the trade - offs that different loads have on distortion, peaking, and noise performance. in gains of 1, 2, and 10, equivalent loads of 1 k ? , 2 k ?, and 5 k ? are shown. with increasing load resistance, the distortion and C 3 db bandwidth improve, while the noise and peaking degrade slightly. r l = 5k? frequency (mhz) normalized closed-loop gain (db) 1 ?8 10 100 1000 03679-a-007 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 r l = 2.5k? ?7 r f = r l = 5k? r f = r l = 2.5k? r f = r l = 1k? g = +2 g = +1 r l = 1k? v s = 5v v out = 0.1v p-p figure 55 . frequency response for various feedback/load resistances disable pin the ad8029 disable pin allows the amplifier to be shut down for power conservation or multiplexing applications. when in the disable mode, the amplifier draws only 150 a of quiescent current. the disable pin control voltage is referenced to the nega tive supply. the amplifier enters power - down mode any time the disable pin is tied to the most negative supply or within 0.8 v of the negative supply. if left open, the amplifier will operate normally. for switching levels, refer to table 6 . table 6 . disable pin control voltage disable pin voltage supply voltage +3 v +5 v 5 v low (disabled) 0 v to <0.8 v 0 v to <0.8 v C 5 v to < C 4 .2 v high (enabled) 1.2 v to 3 v 1.2 v to 5 v C 3.8 v to +5 v
data sheet ad8029/ad8030/ad8040 rev. b | page 19 of 24 circuit considerations pcb layout high speed op amps require careful attention to pcb layout to achieve optimum performance. particular care must be exercised to minimize lead lengths of the bypass capacitors. excess lead inductance can influ ence the frequency response and even cause high frequency oscillations. using a multilayer board with an internal ground plane can help reduce ground noise and enable a more compact layout. to achieve the shortest possible trace length at the inverting inp ut, the feedback resistor, r f , should be located the shortest distance from the output pin to the input pin. the return node of the resistor r g should be situated as close as possible to the return node of the negative supply bypass capacitor. on multilaye r boards, all layers beneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements. this is especially true at the summing junction, i.e., the inver - ting input, C in. extra capacitance at the summing junction can cause increa sed peaking in the frequency response and lower phase margin. grounding to minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. understanding where the current flows in a circuit is cri tical in the implementation of high speed circuit design. the length of the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of the path. fast current changes in an inductive ground r eturn will create unwanted noise and ringing. the length of the high frequency bypass capacitor pads and traces is critical. a parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. because load curren ts flow from supplies as well as from ground, the load should be placed at the same physical location as the bypass capacitor ground. for large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical. power supply bypassing power supply pins are actually inputs to the op amp. care must be taken to provide the op amp with a clean, low noise dc voltage source. power supply bypassing is employed to provide a low imped - ance path to ground f or noise and undesired signals at all frequencies. this cannot be achieved with a single capacitor type; but with a variety of capacitors in parallel the bandwidth of power supply bypassing can be greatly extended. the bypass capacitors have two functions: 1. provide a low impedance path for noise and undesired signals from the supply pins to ground. 2. provide local stored charge for fast switching co nditions and minimize the voltage drop at the supply pins during transients. this is typically achieved with large electrolytic capacitors. good quality ceramic chip capacitors should be used and always kept as close as possible to the amplifier package. a parallel combination of a 0.1 f ceramic and a 10 f electrolytic covers a wide range of rejection for unwanted noise. the 10 f capacitor is less critical for high frequency bypassing and, in most cases, one per supply line is sufficient. the values of c apacitors are circuit - dependant and should be determined by the systems requirements. design tools and technical support analog devices is committed to the design process by providing technical support and online design tools. adi offers technical support via free evaluation boards, sample ics, spice models, interactive evaluation tools, application notes, phone and email support all available at www.analog.com .
ad8029/ad8030/ad8040 data sheet rev. b | page 20 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 56 . 8 - lead standard small outline package, narrow body [soic _n ] (r - 8) dimensions shown in millimeters and (inches) 1.30 bsc compliant to jedec standards mo-203-ab 1.00 0.90 0.70 0.46 0.36 0.26 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 072809-a 0.10 max 1.10 0.80 0.40 0.10 0.22 0.08 3 1 2 4 6 5 0.65 bsc coplanarity 0.10 seating plane 0.30 0.15 figure 57 . 6 - lead plastic surface - mount package [sc70] (ks - 6) dimensions shown in millimeters compliant to jedec standards mo-178-ba 8 4 0 seating plane 1.95 bsc 0.65 bsc 0.60 bsc 7 6 1 2 3 4 5 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0.15 max 0.05 min 1.45 max 0.95 min 0.22 max 0.08 min 0.38 max 0.22 min 0.60 0.45 0.30 pin 1 indicator 8 12-16-2008-a figure 58 . 8 - lead small outline transistor package [sot - 23] (rj - 8) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equi v alents for reference on ly and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45 figure 59 . 14 - lead standard small outline package [soic _n ] (r - 14) dimensions shown in millimeters and (inches) compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 sea ting plane figure 60 . 14 - lead thin shrink small outline package [tssop] (ru - 14) dimensions shown in millimeters
data sheet ad8029/ad8030/ad8040 rev. b | page 21 of 24 ordering guide model 1, 2 minimum ordering quantity temperature range package description package option branding ad8029arz 98 C40c to +125c 8-lead soic_n r-8 ad8029ar-reel 2,500 C40c to +125c 8-lead soic_n r-8 ad8029arz-reel 2,500 C40c to +125c 8-lead soic_n r-8 ad8029ar-reel7 1,000 C40c to +125c 8-lead soic_n r-8 ad8029arz-reel7 1,000 C40c to +125c 8-lead soic_n r-8 ad8029aksz-r2 250 C40c to +125c 6-lead sc70 ks-6 h03 ad8029aksz-reel 10,000 C40c to +125c 6-lead sc70 ks-6 h03 ad8029aksz-reel7 3,000 C40c to +125c 6-lead sc70 ks-6 h03 ad8030ar 98 C40c to +125c 8-lead soic_n r-8 ad8030arz 98 C40c to +125c 8-lead soic_n r-8 ad8030arz-reel 2,500 C40c to +125c 8-lead soic_n r-8 ad8030arz-reel7 1,000 C40c to +125c 8-lead soic_n r-8 ad8030arjz-r2 250 C40c to +125c 8-lead sot23-8 rj-8 h7b ad8030arjz-reel 10,000 C40c to +125c 8-lead sot23-8 rj-8 h7b ad8030arjz-reel7 3,000 C40c to +125c 8-lead sot23-8 rj-8 h7b ad8040arz 56 C40c to +125c 14-lead soic_n r-14 ad8040arz-reel 2,500 C40c to +125c 14-lead soic_n r-14 ad8040arz-reel7 1,000 C40c to +125c 14-lead soic_n r-14 ad8040aruz 96 C40c to +125c 14-lead tssop ru-14 ad8040aru-reel 2,500 C40c to +125c 14-lead tssop ru-14 ad8040aruz-reel 2,500 C40c to +125c 14-lead tssop ru-14 ad8040aruz-reel7 1,000 C40c to +125c 14-lead tssop ru-14 ad8040waruz-reel7 1,000 C40c to +125c 14-lead tssop ru-14 ad8029ar-ebz evaluation board for ad8029, 8-lead soic_n ad8029aks-ebz evaluation board for ad8029, 6-lead sc70 ad8030ar-ebz evaluation board for ad8030, 8-lead soic_n ad8030arj-ebz evaluation board for ad8030, 8-lead sot23-8 ad8040ar-ebz evaluation board for ad8040, 14-lead soic_n ad8040aru-ebz evaluation board for ad8040, 14-lead tssop 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the ad8040w models are available with controlled manufacturing to support the quality and reliability requirements of automotiv e applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
ad8029/ad8030/ad8040 data sheet rev. b | page 22 of 24 notes
data sheet ad8029/ad8030/ad8040 rev. b | page 23 of 24 notes
ad8029/ad8030/ad8040 data sheet rev. b | page 24 of 24 notes ?2003C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03679-0-10/12(b)

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